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TPD7210F 2008-05-12 1 toshiba intelligent power device silicon monolithic power mos integrated circuit TPD7210F power mosfet gate driver for 3-phase dc motor the TPD7210F is a power mosfet gate driver for 3-phase full-bridge circuits that use a charge pump system. the inclusion of a charge pump circuit for high-side drive in side the ic makes it easy to configure a 3-phase full-bridge circuit. features z power mosfet gate driver for 3-phase dc motor z built-in diagnosis function: under-voltage detection z built-in charge pump circuit z package: ssop-24 (300 mil) with embossed-tape packing pin assignment marking (top view) this product has a mos structure and is sensitive to electrostatic discharge. weight: 0.29 g (typ.) TPD7210F lot no. a dot indicates lead(pb)?free part no. (or abbreviation code) sgnd2 sgnd1 fault enb in4 in3 in2 in1 in6 in5 r osc c osc v dd wb vb ub pgnd1 pgnd2 wu vu uu cpv cp2 cp1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
TPD7210F 2008-05-12 2 block diagram / application circuit input-logic circuit reg osc-logic circuit sgnd1 in1 in2 in3 in4 in5 in6 c osc r osc v dd cp1 cp2 cpv fault pgnd1 uu m +b over-voltage protection 5.7v comp osc 32.5v vu wu ub vb wb enb dead-time control v dd +14v comp + f osc =100khz 270pf 62k ? pgnd2 sgnd2 under-voltage detection
TPD7210F 2008-05-12 3 pin description pin no. symbol pin description 1 enb inhibit pin (high active ): by driving this pin low, all outputs can be turned off regardless of input signals. built-in pull-down resistor (100 k ? typ.). 2 r osc this pin sets the oscillation fr equency for the charge pump drive. connect a 62 k ? (typ.) resistor. 3 in1 input pin: it controls the power mosfet connected to uu. built-in pull-down resistor (100 k ? typ.). 4 in2 input pin: it controls the power mosfet connected to vu. built-in pull-down resistor (100 k ? typ.). 5 in3 input pin: it controls the power mosfet connected to wu. built-in pull-down resistor (100 k ? typ.). 6 in4 input pin: it controls the power mosfet connected to ub. built-in pull-down resistor (100 k ? typ.). 7 in5 input pin: it controls the power mosfet connected to vb. built-in pull-down resistor (100 k ? typ.). 8 in6 input pin: it controls the power mosfet connected to wb. built-in pull-down resistor (100 k ? typ.). 9 sgnd1 signal block gnd pin: shared internally with pin 11. 10 cp1 capacitor pin for charge pump. 11 sgnd2 signal block gnd pin: shared internally with pin 9. 12 cp2 capacitor pin for charge pump. 13 v dd power supply pin: when under-voltage (5.5 v typ.) is detected, fault output goes high. on this occasion, all outputs are switching normally, and charge pump circuit does not come to a stop. 14 fault diagnosis output pin: when under-voltage (5.5 v typ.) is detected, fault output goes high. high-side/low-side arm shorting mode, fault output goes high and all outputs are shut down. circuit configuration is n-ch open drain. 15 wb drives the power mosfet connected to the low side of the w phase. 16 pgnd1 power block gnd pin: shared internally with pin 18. 17 vb drives the power mosfet connected to the low side of the v phase. 18 pgnd2 power block gnd pin: shared internally with pin 16. 19 ub drives the power mosfet connected to the low side of the u phase. 20 uu drives the power mosfet connected to the high side of the u phase. 21 vu drives the power mosfet connected to the high side of the v phase. 22 wu drives the power mosfet connected to the high side of the w phase. 23 cpv final stage capacitor pin for the charge pump. 24 c osc this pin sets the oscillation fr equency for the charge pump drive. connect a 270pf (typ.) capacitor.
TPD7210F 2008-05-12 4 truth table (all outputs go to low for input in high-side/low-side arm shorting mode) input output mode no. in1 (uu) in2 (vu) in3 (wu) in4 (ub) in5 (vb) in6 (wb) out uu out vu out wu out ub out vb out wb remarks 01 l l l l l l l l l l l l 02 h l l l l l h l l l l l 03 l h l l l l l h l l l l 04 l l h l l l l l h l l l 05 l l l h l l l l l h l l 06 l l l l h l l l l l h l 07 l l l l l h l l l l l h 08 h l l h l l l l l l l l high-side/low-side arm shorting mode * 09 h l l l h l h l l l h l 120 square wave conducting normal mode 10 h l l l l h h l l l l h 120 square wave conducting normal mode 11 l h l h l l l h l h l l 120 square wave conducting normal mode 12 l h l l h l l l l l l l high-side/low-side arm shorting mode * 13 l h l l l h l h l l l h 120 square wave conducting normal mode 14 l l h h l l l l h h l l 120 square wave conducting normal mode 15 l l h l h l l l h l h l 120 square wave conducting normal mode 16 l l h l l h l l l l l l high-side/low-side arm shorting mode * 17 h h l l l l h h l l l l 18 l h h l l l l h h l l l 19 h l h l l l h l h l l l 20 l l l h h l l l l h h l 21 l l l l h h l l l l h h 22 l l l h l h l l l h l h 23 h h l h l l l l l l l l high-side/low-side arm shorting mode * 24 h h l l h l l l l l l l high-side/low-side arm shorting mode * 25 h h l l l h h h l l l h 26 l h h h l l l h h h l l 27 l h h l h l l l l l l l high-side/low-side arm shorting mode * 28 l h h l l h l l l l l l high-side/low-side arm shorting mode * 29 h l h h l l l l l l l l high-side/low-side arm shorting mode * 30 h l h l h l h l h l h l *: high-side/low-side arm shorting mode is disabled by t he internal logic. fault output goes high (open-drain, high-impedance) *: by driving enb pin low, all outputs can be turned off regardless of input signals. by driving enb pin high, all outputs are switching normally.
TPD7210F 2008-05-12 5 input output mode no. in1 (uu) in2 (vu) in3 (wu) in4 (ub) in5 (vb) in6 (wb) out uu out vu out wu out ub out vb out wb remarks 31 h l h l l h l l l l l l high-side/low-side arm shorting mode * 32 h l l h h l l l l l l l high-side/low-side arm shorting mode * 33 h l l l h h h l l l h h 34 h l l h l h l l l l l l high-side/low-side arm shorting mode * 35 l h l h h l l l l l l l high-side/low-side arm shorting mode * 36 l h l l h h l l l l l l high-side/low-side arm shorting mode * 37 l h l h l h l h l h l h 38 l l h h h l l l h h h l 39 l l h l h h l l l l l l high-side/low-side arm shorting mode * 40 l l h h l h l l l l l l high-side/low-side arm shorting mode * 41 h h h l l l h h h l l l 42 l l l h h h l l l h h h 43 h h l h h l l l l l l l high-side/low-side arm shorting mode * 44 h h l l h h l l l l l l high-side/low-side arm shorting mode * 45 h h l h l h l l l l l l high-side/low-side arm shorting mode * 46 l h h h h l l l l l l l high-side/low-side arm shorting mode * 47 l h h l h h l l l l l l high-side/low-side arm shorting mode * 48 l h h h l h l l l l l l high-side/low-side arm shorting mode * 49 h l h h h l l l l l l l high-side/low-side arm shorting mode * 50 h l h l h h l l l l l l high-side/low-side arm shorting mode * 51 h l h h l h l l l l l l high-side/low-side arm shorting mode * 52 h h h h l l l l l l l l high-side/low-side arm shorting mode * 53 h h h l h l l l l l l l high-side/low-side arm shorting mode * 54 h h h l l h l l l l l l high-side/low-side arm shorting mode * 55 h l l h h h l l l l l l high-side/low-side arm shorting mode * 56 l h l h h h l l l l l l high-side/low-side arm shorting mode * 57 l l h h h h l l l l l l high-side/low-side arm shorting mode * 58 h h h h h l l l l l l l high-side/low-side arm shorting mode * 59 h h h l h h l l l l l l high-side/low-side arm shorting mode * 60 h h h h l h l l l l l l high-side/low-side arm shorting mode * 61 h h l h h h l l l l l l high-side/low-side arm shorting mode * 62 l h h h h h l l l l l l high-side/low-side arm shorting mode * 63 h l h h h h l l l l l l high-side/low-side arm shorting mode * 64 h h h h h h l l l l l l high-side/low-side arm shorting mode * *: high-side/low-side arm shorting mode is disabled by t he internal logic. fault output goes high (open-drain, high-impedance) *: by driving enb pin low, all outputs can be turned off regardless of input signals. by driving enb pin high, all outputs are switching normally.
TPD7210F 2008-05-12 6 absolute maximum ratings (t a = 25c) characteristic symbol rating unit remarks power supply voltage v dd(1) ? 0.5 to 30 v power supply voltage v dd(2) 45 v pulse width 200ms i source 1 output current i sink 1 a pulse width 10 s input voltage v in , v enb ? 0.5 to 7.0 v fault pin voltage v fault 30 v pgnd pin negative voltage p gnd (-) ? 0.5 v negative voltage that can be applied to pgnd pin (reference to sgnd pin) output pin negative voltage v out(-) ? 0.5 v negative voltage that can be applied to uu, vu,wu,ub,vb and wb pins (reference to sgnd pin) fault pin current i fault 5 ma 0.8 power dissipation p d 1.2 (note2) w operating temperature t opr ? 40 to 125 c junction temperature t j 150 c storage temperature t stg ? 40 to 150 c note1 : using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operat ing temperature/current/voltage, etc. ) are within the absolute maximum ratings and the operating ranges. please design the appropriate reliability upon reviewing the toshiba semiconductor reliability handbook (?handling precautions?/?derating concept and methods?) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). thermal resistance characteristic symbol rating unit 156.3 junction to ambient thermal resistance r th (j-a) 104.2 (note2) c / w note2: when the device is mounted on a 60 mm 60 mm 1.6 mm glass epoxy pcb
TPD7210F 2008-05-12 7 electrical characteristics (unless otherwise specified, t a = ? 40 to 125c, cp1, 2 = 0.1 f, r osc = 62k ? , c osc = 270pf) characteristic symbol test circuit condition min typ. max unit remarks operating supply voltage (note3) v dd(opr) ? ? 4.5 13.5 18 v i dd(1) ? v dd = 13.5 v ? ? 7 oscillation circuit stops supply current i dd(2) ? v dd = 13.5 v, v in1 to v in6 = 0 v, cp1,2 = 0.1 f ? ? 9 ma when oscillation circuit is operating f = 100 khz, mean current v ih 3.5 ? ? in1 to in6 and enb high-level input voltage input voltage v il ? v dd = 7 to 18 v, i o = 0 a ? ? 1.5 v iin1 to in6 and enb low-level input voltage i ih v dd = 7 to 18v, v in = 5 v ? ? 200 a input current i il ? v dd = 7 to 18 v, v in = 0 v ? 10 ? 10 a in1 to in6, enb input current (per one input) v dd = 7 v, v in1 to v in6 = 0 v v dd +10.9 v dd +11.9 ? v v cpv 3 (v dd ? v f ) v cpv denotes cpv pin voltage. (reference to sgnd pin) v dd = 13.5 v, v in1 to v in6 = 0 v v dd +12 v dd +14 v dd +16 v charge pump voltage (note4)(note5) v cpv ? v dd = 18 v, v in1 to v in6 = 0 v v dd +12 v dd +14 v dd +16 v v cpv denotes cpv pin voltage. (reference to sgnd pin) v oh(h1) v dd = 7v, v in = 5v, i o = ? 10ma ? v dd + 9.9 ? v oh(h2) v dd = 13.5 v, v in = 5 v, i o = ? 10 ma ? v dd + 12 ? high-side high-level output voltage v oh(h3) v dd = 18 v, v in = 5 v, i o = ? 10 ma ? v dd + 12 ? high-side high-level output voltage drop v drop ? v in = 5 v, i o = ? 10 ma, v drop = v cpv ? v oh ? 2 3 high-side low-level output voltage v ol(h) ? v dd = 7 to 18 v, v in = 0 v, i o = 0 a ? ? 0.1 uu, vu and wu pin voltage (reference to sgnd pin) *measuring single pulse low-side high-level output voltage v oh(l) ? v dd = 7 to 18v, v in = 5v, i o = ? 10ma v dd - 0.1 v dd ? low-side low-level output voltage v ol(l) ? v dd = 7 to 18 v, v in = 0 v, i o = 0 a ? ? 0.1 v ub, vb and wb pin voltage (reference to sgnd pin) r source v dd = 13.5 v, v in = 5 v, i o = ? 0.5 a ? 7 10 output on resistance r sink ? v dd = 13.5 v, v in = 0 v, i o = 0.5 a ? 4.5 10 ? uu, vu, wu, ub, vb and wb output resistance pulse width 10 s
TPD7210F 2008-05-12 8 characteristic symbol test circuit condition min typ. max unit remarks detection v dduv 5.0 5.5 6.0 under- voltage detection hysteresis ? v dduv ? ? ? 0.5 ? v under voltage detection voltage and hysteresis (v dd voltage detected) turn-on delay time t d (on) ? 0.25 1 turn-on time t on ? 0.5 2 turn-off delay time t d (off) ? 0.25 1 switching times turn-off time t off 1 v dd = 13.5 v, v cpv = 13.5 v, c out = 12400 pf, r g = 47 ? ? 0.5 2 s uu, vu, wu, ub, vb and wb switching times dead time (note 6) t dead ? v dd = 13.5 v, t dead = t off ? t d(on) ? 0.25 1 s oscillating frequency f osc ? v dd = 7 to 18v, r osc = 62 k ? , c osc = 270 pf 80 100 120 khz fault output voltage v fault ? v dd = 7 to 18 v, i fault = 1 ma ? ? 0.8 v fault pin low ? level voltage (open ? drain) fault output leakage current i fault ? v dd = 7 to 18 v, v fault = 18 v ? ? 10 a fault output delay time t d(fault) ? ? ? ? 1 s note3 : on-off output control, fault output and charge pump circuit operate from v dd 4.5v. however, charge pump voltage (cpv voltage) decreases by there are a lot of output currents in the c ondition with a low power supply voltage (v dd ). it may be not enough voltage (v gs ) to drive external power mosfet. be careful enough when using it . note4 : when converting foward voltage of the charge pump circuit diode by 0.7v. please use the diode of high-speed type (trr 100ns). note5 : about the charge pump voltage so as not to apply over-voltage to the gate-source voltage(v gs ) of external power mosfet, and so as to become the best driving voltage,the clamping circuit is built into. when the cpv voltage reaches the value, so as not to apply over-voltage, the oscillatio n logic circuit of the charge pump is stopped. cpv voltage v dd voltage 3 vdd - 3 v f @v in1 to v in6 = 0v (v f : diode forward voltage) cpv voltage area :v cpv =3 v dd - 3 v f area :v cpv clamp=v dd + 14v typ. area :v cpv clamp=32.5v typ. (35v max) (8) (18) 4.5
TPD7210F 2008-05-12 9 note6 : about the dead time high-side/low-side arm shorting mode is disabled by t he internal logic. all outputs can be turned off. the deadtime of this product is 1 s. that doesn't contain dea dtime of external power mosfet. please set the deadtime of the input signal after considering t he switching time of external power mosfet. note7 : about the direct input method of the charge pump oscillation frequency by the oscillation signal from the outside to c osc it is possible to set up the charge pump oscillation. as this method, please input the signal to c osc after v dd becomes over 9v. (v cosc 5.5v) moreover, please use the terminal r osc by the resistance unconnection (open). when the cpv voltage reaches up to the clamping voltage, though the signal is input to c osc , the movement of the charge pump (oscillation) stops. test circuit 1 switching times example of measuring uu output truth table in enb vout fault state l l l l h l l l l h l l h h h l normal l l l h h l l h l h l h h h h h v dd under-voltage detection l l h high-side h low-side h h l h upper and lower short- circuit input detection t r 0.1 st f 0.1 s t d(on) t on t d(off) t off v dd =13.5v v dd - 3v (v dd - 3v) 90% (v dd - 3v) 10% input waveform v in 50% 5v(100%) output waveform v out 90% 10% 90% 10% 23 13 3 9 11 20 18 16 in1 v dd cpv uu sgnd1 47 12400pf v 1 enb 5v 13.5v p. g. sgnd2 pgnd1 pgnd2 ? when under-voltage (5.5v typ.) is detected, only fault outputs ?h". neither the output nor the operation of the charge pump circuit stops(off). ? when a in-phase high side and the low si de input are the ?h" levels, all the outputs be made ?l" level, and the ?h" level is output to fault.
TPD7210F 2008-05-12 10 timing chart power supply voltage v dd high-side input low-side input enb signal charge pump circuit high-side output low-side output fault output uv detect (5.5v typ.) uv recover y (6.0v typ.) operating supply voltage(4.5v min) output l output l stop uv detect uv detect high-side/low-side arm inputs shorting is detected high-side/low-side arm inputs shorting is detected
TPD7210F 2008-05-12 11 input voltage v ih , v il (v) power supply voltage v dd (v) v ih , v il - v dd junction temperature t j (c) i dd(1) - t j supply current i dd(1) (ma) 10 8 6 4 2 0 -80 -40 0 40 80 120 160 v dd =13.5v oscillation circuit stops junction temperature t j (c) i dd(2) - t j supply current i dd(2) (ma) -80 -40 0 40 80 120 160 0 2 4 6 8 10 v dd =13.5v f osc =100khz cp1,2=0.1 f v in1 to v in6 =0v power supply voltage v dd (v) i dd(2) - v dd supply current i dd(2) (ma) power supply voltage v dd (v) i dd(1) - v dd supply current i dd(1) (ma) 10 8 6 4 2 0 0 4 8 12 16 20 t j =25c oscillation circuit sto p s 10 8 6 4 2 0 0 4 8 12 16 20 t j =25c f osc =100khz cp1,2=0.1 f v in1 to v in6 =0v t j =25c 5 4 3 2 1 0 0 4 8 12 16 20 input voltage v ih , v il (v) junction temperature t j (c) -80 -40 0 40 80 120 160 5 4 3 2 1 0 v dd =13.5v v ih v il v ih v il v ih , v il - t j
TPD7210F 2008-05-12 12 high-side high-level output voltage drop v drop (v) power supply voltage v dd (v) v drop - v dd v cpv - v dd charge pump voltage v cpv (v) 40 32 24 16 8 0 v oh(h) , v oh(l) - v dd high-level output voltage v oh (v) i ih - t j input current i ih ( a) 200 160 120 80 40 0 4 3.2 2.4 1.6 0.8 0 0 4 8 12 16 20 junction temperature t j (c) -80 -40 0 40 80 120 160 v dd =13.5v v in , v enb =5v one input pin -80 -40 0 40 80 120 160 junction temperature t j (c) 0 4 8 12 16 20 power supply voltage v dd (v) -80 -40 0 40 80 120 160 40 32 24 16 8 0 charge pump voltage v cpv (v) junction temperature t j (c) v cpv - t j v in1 to v in6 =0v v dd =18v v dd =13.5v v dd =7v v dd =4.5v t j =25c v in1 to v in6 =0v power supply voltage v dd (v) 0 4 8 12 16 20 40 32 24 16 8 0 t j =25c i o =-10ma measuring single pulse low-side output high-side output t j =25c i o =-10ma v dd =13.5v i o =-10ma v drop - t j high-side high-level output voltage drop v drop (v) 4 3.2 2.4 1.6 0.8 0
TPD7210F 2008-05-12 13 ? v dduv - t j 1 0.8 0.6 0.4 0.2 0 v dduv - t j under-voltage detection v dduv (v) 7 6.8 6.2 5.8 5.4 5 junction temperature t j (c) -80 -40 0 40 80 120 160 -80 -40 0 40 80 120 160 junction temperature t j (c) 1 0.8 0.6 0.4 0.2 0 switching times (high-side output) t d(on) , t on , t d(off) , t off ( s) switching times - v dd power supply voltage v dd (v) 0 4 8 12 16 20 uv detect uv recover y under-voltage detection hysteresis ? v dduv (v) junction temperature t j (c) -80 -40 0 40 80 120 160 power supply voltage v dd (v) t on t off t d(off) t d(on) v dd =v cpv r g =47 ? , c out =12400pf t j =25c high-side output switching times (high-side output) t d(on) , t on , t d(off) , t off ( s) switching times - t j -80 -40 0 40 80 120 160 t off t on t d(off) t d(on) 1 0.8 0.6 0.4 0.2 0 0 4 8 12 16 20 1 0.8 0.6 0.4 0.2 0 switching times (low-side output) t d(on) , t on , t d(off) , t off ( s) switching times - v dd switching times - t j junction temperature t j (c) switching times (low-side output) t d(on) , t on , t d(off) , t off ( s) v dd =v cpv =13.5v r g =47 ? , c out =12400pf high-side output v dd =v cpv r g =47 ? , c out =12400pf t j =25c low-side output t off t on t d(off) t d(on) 1 0.8 0.6 0.4 0.2 0 t off t on t d(off) t d(on) v dd =v cpv =13.5v r g =47 ? , c out =12400pf low-side output
TPD7210F 2008-05-12 14 125 115 105 95 85 75 f osc - v dd oscillating frequency f osc (khz) 125 115 105 95 85 75 0 4 8 12 16 20 junction temperature t j (c) -80 -40 0 40 80 120 160 power supply voltage v dd (v) t j =25c r osc =62k ? , c osc =270pf f osc - t j oscillating frequency f osc (khz) v dd =13.5v r osc =62k ? , c osc =270pf 0.5 0.4 0.3 0.2 0.1 0 fault output voltage v fault (v) v fault - v dd power supply voltage v dd (v) 0 4 8 12 16 20 i fault =1ma t j =25c v fault - t j fault output voltage v fault (v) 0.5 0.4 0.3 0.2 0.1 0 -80 -40 0 40 80 120 160 junction temperature t j (c) i fault =1ma v dd =13.5v 1.4 1.2 1.0 0.8 0.6 0 power dissipation p d (w) p d - t a ambient temperature t a (c) -40 0 40 80 120 160 60mm 60mm 1.6mm when a device is mounted on glass epoxy pcb. without pcb 0.4 0.2
TPD7210F 2008-05-12 15 usage precautions precautions on dry packing after unpacking dry or moisture-proof packing, make sure the device is mounted in place within 48 hours at a temperature and humidity of 30c and 60% rh or le ss. because the device is emboss-taped and cannot be processed by baking, always be sure to use it within the said allow able time after unpacking. standard tape packing quantity: 2000 devices / reel (el1).
TPD7210F 2008-05-12 16 package dimensions weight: 0.29 g (typ.) unit: mm ssop24-p-300-1.00c
TPD7210F 2008-05-12 17 restrictions on product use 20070701-en general ? the information contained herein is subject to change without notice. ? toshiba is continually working to improve the quality and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity an d vulnerability to physical stress. it is the responsibility of the buyer, when utilizing toshiba produc ts, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most recent toshib a products specifications. also, please keep in mind the precautions and conditions set forth in the ?handling guide for semiconduct or devices,? or ?toshiba semiconductor reliability handbook? etc. ? the toshiba products listed in this document are in tended for usage in general electronics applications (computer, personal equipment, office equipment, measuri ng equipment, industrial robotics, domestic appliances, etc.).these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfuncti on or failure of which may cause loss of human life or bodily injury (?unintended usage?). unintended usage incl ude atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, et c.. unintended usage of toshiba products listed in his document shall be made at the customer?s own risk. ? the products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. ? please contact your sales representative for product- by-product details in this document regarding rohs compatibility. please use these products in this document in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances. toshiba assumes no liability for damage or losses occurring as a result of noncompliance with applicable laws and regulations.

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